Digital-to-analog converters (DACs) have long been used in a wide variety of applications, including communications, optical outputs, audio outputs, video displays, medical monitors, motors, radio transmitters, temperature measurement and control, seismic measurement, sonar and the like. In many applications, analog signals are generated by a sensor or other device and then digitized by analog-to-digital converters (ADCs). The digitized signals are then processed, in a manner that depends upon the application, and converted back to analog signals by DACs.
For many applications, such as communications, a current-steering DAC is often used. A basic principle of current steering DACs includes summing the currents from current sources according to the digital input signals received by the DAC. Due to their extensive use, the impairments to the performance of current-steering DACs are well studied and understood. An ideal DAC would produce an analog output voltage or analog output current that is proportional, or has a linear relation in a transfer function, to the digital input code or digital input words. Therefore, nonlinearity may be considered to be undesirable in DACs, and may be described in terms of differential-nonlinearity (DNL) and integral-nonlinearity (INL). DNL may be described as the deviation between an ideal output level step change, which may be a least significant bit (LSB) step change, and the actual change in output levels resulting from two adjacent parts of the digital input code. INL may be described as the maximum deviation from the best-fit line of the DAC analog output plotted against the digital input code on a transfer function. It has been found that the random and systematic mismatch of current sources of current-steering DACs may be a key contributor to the DNL and INL of the DACs.
It has also been found that the mismatch of the current sources can be relatively easily removed either by using larger device size and layout patterning, or by various calibration techniques to make sure the weights of the current sources are either the same or binary scaled. The linearity impairment due to finite (cell) output impedance, which is a combination of output resistance and capacitance, has also been well characterized. In order to reduce the impact of the code-dependent output resistance, the output resistance may be increased by using cascode schemes. Specifically, when the output resistance of the current source is large enough, the effect of code-dependent output resistance can be negligible given the required linearity in terms of INL.
However, there may still be significant challenges when employing the cascode scheme. First, in advanced deep-submicron technologies, the supply voltage may drop significantly during operation of the device, which can cause problems since cascoding needs sufficient headroom to operate. Second, parasitic capacitance, which may be the main culprit of output impedance lowering, may be dominating when the output signal frequency of the DAC is high. An output signal frequency may be considered to be high when the imaginary part of the output impedance becomes approximately equal to the real part of the output impedance.
Although to some degree using cascoding may alleviate the problem, it may not solve the problem properly. One of the major limiting factors in terms of the effective-number-of-bits (ENOB) at high (signal) frequency may be because the output impedance, at high frequency, is code-dependent and is not high enough.